Method for power estimation for virtual prototyping models for semiconductors

ABSTRACT

The present invention may comprise an apparatus and method for calculating power consumption, including a unit for generating a clock-level analysis without synthesis of an algorithm description and calculating operating ratios of storage elements and arithmetic units. The invention may also comprise a method for estimating the power to be consumed by a SystemC model. By estimating this value, a user may gauge the amount of power a specific semiconductor design might consume, once manufactured into a chip.

CROSS-REFERENCE TO RELATED APPLICATION

The application claims priority from U.S. Provisional Patent ApplicationNo. 61/696,213, filed Sep. 2, 2012, the contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates generally to virtual prototyping.Specifically, the invention relates to a method for predictivesimulation and power estimation of microdevices and microsystems.

Portable and high-density micro-electronic devices make powerdissipation of very large scale integrated (VLSI) circuits a criticalconcern. Because of limited battery life, reliability issues, andpackaging and cooling costs, power consumption for devices is a criticaldesign concern. To avoid issues associated with excessive powerconsumption, computer design helps to estimate power consumption of VLSIdesigns.

The rapid progress in microsystems technology is increasingly supportedby specific modeling methods and dedicated simulation tools. Thesemethods not only enable the visualization of fabrication processes andoperational principles, but also assist a designer to make decisions forfinding optimized microstructures under relevant technological andeconomical constraints. Currently efforts are being made towards usingsimulation platforms for the predictive simulation of microsystems,i.e., the “virtual fabrication” and “virtual experimentation andcharacterization” on a computer.

A digital semiconductor chip is often designed using a HardwareDescription Language (HDL) such as Verilog or VHDL (Very High-SpeedIntegrated Circuit, VHSIC, Hardware Description Language). To verifythat the design operates according to the design specification, it mustbe simulated in a verification environment. These simulations aretypically done using commonly available simulation tools such as NC Sim(from Cadence) and VCS (from Synopsys). Other simulators from variousdifferent vendors may also be used. As these simulations run in a“cycle-accurate” mode, they tend to be very accurate in representing thebehavior of the design. In “cycle accurate mode,” the real clock signalthat is expected to be provided to the semiconductor chip is supplied tothe design during simulations. Since the real clock signal cycles manytimes during simulations, the simulations tend to be very slow, as eachclock cycle (or “tick”) necessitates evaluation of the simulator events.Typically, modern digital design involves clock signal frequencies ofseveral million cycles per second to several billion cycles per second.Thus, simulating real world conditions which happen over several minutesbecomes extremely slow.

One of the methods to speed up these simulations and increase thesimulation performance is to represent the semiconductor design in ahigher abstraction level. The higher abstraction representation of thesemiconductor design will use the concept of Transaction Level Modeling(or TLM) to model the behavior of the semiconductor design. Such ahigher abstraction model might be written with a language like SystemC,SystemVerilog, C, C++ or any other suitable language. This higherabstraction model is known as a “Virtual Prototype” of the semiconductordesign. The virtual prototype can then be simulated in a SystemCsimulator (many simulation tools are available from various vendors).The simulations in a SystemC/TLM simulator tend to be much faster, up to200 or 300 times faster as compared to the semiconductor designsimulations.

The acceleration is due to the simulations run in one of the followingmodes prescribed by the standards committee for SystemC/TLM modeling,Accelera.

-   -   A) “untimed”—where no clock signal used.    -   B) “approximately timed”—different transaction “phases” are used        to time the model (clock signal is used rarely in this mode).    -   C) “loosely timed”—more transaction phases are used than in B        (clock signal is used occasionally in this mode).

In A, the clock signal is not used at all. In B, the clock signal israrely used; instead the model relies on the “start” phase of atransaction or event occurring within the block and the “end phase” ofthat transaction or event. In C, more phases of the transaction are usedto time the model (start phase, active phase, acknowledgement phase, endphase, etc. More phases may be defined by the user as required).

There is no “cycle accurate” mode prescribed by Accelera when buildingand simulating a virtual prototype. Cycle accurate mode is the mostaccurate mode used to simulate the real semiconductor design using thereal clock signal, as described previously. Accelera usually recommendsthat the number of modes be no greater than three. The present inventionmay comprise a number of modes greater than three.

The challenge: In a semiconductor design built using an HDL (likeVerilog or VHDL) it is easier to estimate the power consumption based onthe frequency of the clock signal that the design runs on, and severalother parameters inside the design. This results in a fairly accurateestimation of the power that the design might consume, once it isapplied into a real world semiconductor chip. However, in a virtualprototype of the semiconductor design, any power estimation will not beaccurate. The reason is that semiconductor design simulations always runin a “cycle-accurate” mode, using every clock tick of the real clocksignal. In the virtual prototype, in the any of the timing modes:untimed, approximately timed or the loosely timed, the clock used is anapproximation of the real clock signal.

Power estimation can be hampered in complexity, time, and cost, byengaging in model synthesis. Power estimation without performing themodel synthesis step, has been avoided due to the industry's failure todevelop a method of estimating power that excludes model synthesis. Ifthe power estimation process could be performed without model synthesis,then time and costs could be decreased.

There is a need to give an accurate estimation of the power consumed ina virtual prototype, because today's low-power semiconductor designsdemand an estimation of power from the virtual prototyping systems. Thevirtual prototype is typically built very early on in the designprocess. Thus, if the prototype could provide an accurate estimation ofpower, it helps the user to make better design choices, before thedesign gets finalized. Also, the method should look towards streamliningwhere feasible, such as concerning synthesis steps.

SUMMARY OF THE INVENTION

In one aspect of the present invention, a method for measuring power ina virtual prototype for a model semiconductor design may comprise;identifying, within a netlist representing an integrated circuit, one ormore transistors coupled to a voltage supply for which to estimate poweras applied to a virtual prototype representing the integrated circuit,generating a respective measurement statement for each of the one ormore transistors, wherein the respective measurement statement is usableby a circuit simulation tool to measure the power consumed within thevirtual prototype of a design block during a simulation of the virtualprototype representing the integrated circuit, without synthesizing themodel, and, creating a measurement file and placing respectivemeasurement statements within the measurement file, wherein themeasurement file is usable by the circuit simulation tool for performingthe simulation of the integrated circuit.

In another aspect of the present invention, a method for powerevaluation may comprise (sometimes for each respective module of aplurality of modules); providing an Electronic System Level CircuitDescription (ESLCD) containing a plurality of operations of modules foranalysis, reviewing the SLCD and identifying those operations of modulesof the ESLCD that are equivalent to a previously analyzed case, a casecomprising an operation of a module, and those operations of modules ofthe ESLCD that have no equivalent previously analyzed case, for eachoperation of module of the ESLCD that is equivalent to a previouslyanalyzed case, retrieving a power macro-model of the previously analyzedcase from memory and assigning that power macro-model to that operationof module in the ESLCD, for each operation of module of the ESLCD thathas no equivalent previously analyzed case, generating a powermacro-model for each operation of module and assigning that generatedpower macro-model to that operation of module in the ESLCD, using theplurality of power macro-models, sample input vectors and sample outputvectors, evaluating the power consumption of each of the operation ofmodules in the ESLCD and summing the power consumption of each of theoperation of modules to provide a system level power estimate, whereinthe cases are defined by a circuit description and a context of theinput stimuli under which the circuit is exercised, wherein the contextof the input stimuli under which the circuit is exercised furthercomprises a testbench description, the testbench description partitionedinto segments, and producing a monitor file wherein the monitor filecomprises the test bench description and a pair of print statementsassociated with each segment in the testbench description, in which theprint statements cause the simulation time of execution of the printstatement to be printed to a designated file along with an identifier ofthe segment.

These and other aspects, objects, features and advantages of the presentinvention, are specifically set forth in, or will become apparent from,the following detailed description of an exemplary embodiment of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects of the present invention will become moreapparent by the following detailed description of exemplary embodimentsthereof with reference to the attached drawings, in which:

FIG. 1 is a schematic block diagram of a semiconductor design block,according to an embodiment of the present invention;

FIG. 2 is a block diagram of a virtual prototype of a semiconductordesign block, according to an embodiment of the present invention;

FIG. 3 is a block diagram of an exemplary method of power estimationincluding interaction between a power estimation block and a virtualprototype block, according to an embodiment of the present invention;

FIG. 4 is a flow chart of an exemplary method of power estimation,according to a further embodiment of the present invention; and

FIG. 5 shows a typical computer system for employing the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description is of the best currently contemplatedmodes of carrying out the invention. The description is not to be takenin a limiting sense, but is made merely for the purpose of illustratingthe general principles of the invention, since the scope of theinvention is best defined by the appended claims.

Model synthesis, such as logic synthesis, entails costs, timeexpenditure, and manpower. For power estimation using model synthesis ofvirtual prototypes, wherein architectural exploration and system levelperformance analysis are important goals, power estimation may beachieved without full model synthesis, saving excessive costs, time, andmanpower. This invention provides a method to estimate power in avirtual prototype without model synthesis.

A virtual prototype of a semiconductor design consists of many blocks,each performing a specific task. Each block can have either a singleclock, or multiple clocks supplied to it. Every block might have asingle or multiple voltages applied to it. The blocks also might getturned off or on, be in sleep mode, active state, and such. Thus, thepower consumed varies widely. This is called dynamic power consumed. Ina quiescent state, the blocks still consume some power due to theleakage in the transistors that make up the chip. This is called leakageof power or static power consumption. Both must be taken into theestimation of the total power consumed as a whole inside the design.

Static Power or “Ps” can be measured by

Ps=(leakage power estimation per gate)×(number of gates expected in theblock).

A power estimation system 100, involving a semiconductor design block110 is shown in FIG. 1. A clock frequency signal 102 may be alternatelyrepresented by f. A voltage 104 that is expected to be supplied may berepresented by V. Load capacitance 106 expected for block 110 may berepresented by C. The average switching gates 108 in the block 110 maybe measured per clock tick and represented as a. Pd may represent thedynamic power consumed by block 110.

The relationship may be understood as the dynamic power is equal to theproduct of the load capacitance, the square of the voltage, thefrequency, and the average switching gates value.

Pd=C×V ² ×f×a

The above representation is a model of the relationship when the blockbecomes part of a chip.

The total power dissipation for a block is thus estimated as:

Total Power, P=Pd+Ps.

The above is for a semiconductor design block and not the virtualprototype of the block.

In a virtual prototype of the above block, the clock is used as areference to synchronize the behavior of the block at approximateintervals, thus deviating significantly from the true frequency of theclock. There is also no voltage, leakage power, average switching gates,or loading capacitance information available in a virtual prototype.

As shown in the system 120 displayed in FIG. 2, the clock signal 122used in a virtual prototype looks much different than the clock signalused in the real design, shown in FIG. 1. An approximation of the realclock is used, to speed up the simulations. This directly impacts theclock frequency “f” in the dynamic power equation, and gives rise tovery imprecise calculation of Pd, or dynamic power. Reference clocksignal 124 may serve to calibrate, or standardize, variations in theclock signal 122 as handled within the virtual prototype 126.

Due to this approximation of the clock signal in the virtual prototype126, combined with the lack of voltage, load capacitance, average numberof switching gates and leakage power parameters, the block's powerconsumption cannot be estimated accurately.

To accurately estimate the power in a virtual prototype, theconstruction must be enhanced, by adding one or more of the following:

-   -   1. A “Power Estimation Block” (or P.E. block) that works in        conjunction with the virtual prototype.    -   2. The real clock signal must be supplied to the Power        Estimation Block. This is the same clock that is supplied to the        design on which the virtual prototype is based, not the        approximated clock.    -   3. The voltage consumed by the block must be supplied as a        parameter to the power estimation block.    -   4. The load capacitance expected for the block.    -   5. The leakage power per gate that is expected within the design        must be supplied as a parameter.    -   6. Expected number of gates for the block.    -   7. Any additional power consuming parts that might be specific        to the design might also be supplied.    -   8. A means of communication between the virtual prototype and a        “Power Estimation Block” that works in conjunction with the        virtual prototype, called the P.E. Communication channel. This        communication might be achieved by means of software methods or        functions.    -   9. Increase the number of timing modes from the three modes        (untimed, approximately timed and loosely timed) to include        several intermediate modes in addition to the ones mentioned. In        addition, include a cycle-accurate mode wherein a real clock        signal is used.    -   10. A means of controlling the various timing modes in the        virtual prototype.    -   11. To support the means of controlling, a control “knob” might        be presented to the user in a Graphical User Interface or GUI,        for ease of control. The control knob may serve to allow the        user to select various timing modes in which the virtual        prototype will operate.

Further details on each step are now provided below, in reference to thesystem 130 in FIG. 3. The power estimation block or P.E. block 136 isassociated with each virtual prototype block 134. The power estimationblock 136 works in conjunction with the virtual prototype block 134 todetermine what power state the block is currently in, such as, SleepState, Active State, Reset State, Power-Off State, and such. The P.Eblock 136 may determine the power state by means of the P.E.communication channel 138. The P.E. communication channel 138 may beimplemented by using any suitable software language such as SystemC,SystemVerilog, C, C++ or equivalent, using functions, methods orcallbacks. The frequency signal 132 may be compared with the real clocksignal 140.

The real clock signal 140 that is expected to be supplied to the designon which the virtual prototype is based must also be supplied to theP.E. block 136. The P.E. block 136 uses the real clock signal 140 toestimate how much power might be consumed by the virtual prototype indifferent timing modes. The voltage 142 that is expected to be suppliedto the design must also be supplied to the P.E. block 136. The P.E.block 136 uses the voltage as a parameter as one of the inputs whenestimating the power consumed in the virtual prototype. The loadingcapacitance 146 should be supplied to the P.E. block. The leakage powerper gate 144 that is expected in the design is supplied to the P.E.block 136. Other specific features that affect the power for the PowerEstimation Block 136 may be used. An expected number of gates may besupplied to the P.E. block 136.

Any additional information that is relevant to power estimation, such assome specific and unique features within the design block that mightaffect the power consumption more than normal might be supplied by theuser to the P.E. block 136. Some examples (but not limited to thisexample) of these specific features might be the presence of floating,or un-driven output pins, which typically result in a large power draw.The P.E. block may use this information when estimating the powerconsumed by the virtual prototype.

A communication channel 138 between the P.E. block 136 and the virtualprototype block 134, to keep the P.E. block 136 informed of the currentpower state of the virtual prototype block 134, such as (but not limitedto) clock frequency changes, power states such as Sleep State, OffState, Active State, quiescent state, outputs not being actively driven,and such. These are used by the P.E. block 136 to estimate the powerconsumed by the virtual prototype block 134 during the simulations. Thischannel might be based on software functions, methods or callbacks. Anyother suitable means of communication may also be used.

Several intermediate timing modes may have additional gradations betweenthe untimed, approximately timed, and loosely timed modes currentlysuggested by Accelera, the standards organization for virtual prototypemodeling. In addition, a cycle-accurate mode may be used with the realclock signal as used by the design block.

A means of controlling the various timing modes should be present in thevirtual prototype. This should allow the user to seamlessly choosebetween untimed modes on one end of the control, to the cycle-accuratemode on the other end of the control. Other timing modes such asapproximately timed and loosely timed modes will be available, to bechosen in the middle of the control band. In addition, more gradationsin the timing modes (semi-loosely timed, semi-approximately timed, semiuntimed and such) should also be made available, though these are notdefined by the standards committee Accelera currently. These“intermediate” timing modes will give greater flexibility to the user inchoosing a timing mode.

The P.E. block 136 may have a control “switch” for the user to turn iton or off. For every virtual prototype block, a P.E. block may be built.For multiple instances of the same virtual prototype, there will existmultiple instances of the same P.E. block 136, operating independently.The Power Estimation block 136 may be built using power estimationalgorithms designed specifically for use in a virtual prototypingplatform, as described in detail earlier regarding the power estimationequations. These algorithms may be built using any of the suitablesoftware languages available today, like C, C++, System C, SystemVerilog or other such languages.

The power that is estimated may be represented in a Graphical UserInterface. During simulations, the estimated numerical entity may becontinually updated by the P.E. block 136 and made available to the userin the Graphical User Interface in the form of a numbered, color-codedband, or any other visually useful method.

A virtual prototyping platform may include one or more virtualprototypes of the many blocks that make up a semiconductor chip. TheP.E. blocks associated with the prototypes may be used to estimate thetotal power consumed within that platform, or a sub-section of theplatform. A sub-section might consist of a subset of the blocks withinthe platform. Thus the total power that is consumed in a system may beestimated from the summation of the individual power estimates from aset of blocks that constitute the virtual prototype platform.

A method 400 for estimating power consumption is shown in FIG. 4. Themethod may commence with Step S402 of building a model. Step S404 maycomprise creating a test case or test cases for generating a stimulus.Generating a clock frequency signal may comprise Step S406. Anotherstep, Step S408 may comprise stimulating test cases using acycle-accurate timing mode. Still another step, S410 may comprisestoring a power estimated value.

Another Step S412 may comprise simulating test cases using other timingmodes, such as untimed modes, loosely timed modes, and any othersuitable modes. At any time a Step S414 may comprise using powerinformation. The power information may be stored in memory for thesimulation. The power information may come from elsewhere, such asimmediately from a processer without being stored, or from any othersuitable source. Yet another Step S416 may comprise writing powerinformation to a log file. The power information may be written atpre-determined intervals, which may permit output, such as line graphs,bar graphs, histograms, or other types of output to display the historyof user power consumption.

The present invention may be practiced in several manners, includingwith various computer languages. SystemC is one particular language thatis advisable for practicing the present invention. A SystemC model is amodel of Register Transfer Level (“RTL”) design as the model does nothave gates. Thus, one may use the following methodology to estimate theequivalent number of “gates” expected in a particular SystemC model.

An object file may be produced in the compilation stage of a SystemCmodel or a parsing system may be used to parse the SystemC modeldescription to generate a token file. From this object/token file, onemay deduce the number of memory variables contained in a model. Forexample, a 32 bit “reg” type signal in the RTL may become a 32 bit wide“int” in a SystemC model. A single bit “reg” type may become a typesc_logic which may be only 1 bit wide in SystemC. From this operation, atable may be built for each date type existing in System versus RTL. Notall variables in SystemC may be thought of as “reg” types in RTL.Usually, only variables appearing in the Left Hand Side (“LHS”) of anyequations or assignments inside a clocking class in SystemC should beconsidered as “reg” types in RTL.

Each “reg” type may now be represented as a SystemC data type. Each“reg” type may be considered as comprising one “D” type flip-flop whenthe RTL becomes a chip. Thus, the system may gather information on howmuch power is consumed by a “D” type flip-flop from a technologylibrary. From the information on power estimation, the system mayextrapolate the power estimation to other SystemC models.

A number of “virtual D type flip flops” in a SystemC model=32 in int,“n” in sc_unit<n>, sc_bv<n>, one in sc_logic. Total power consumed maybe calculated as:

Number of “virtual D type flip-flops” nd times power estimation value ofa single D type flip flop from the technology library, “pd.”

-   -   Total dynamic power consumed per clock event in the “virtual D        flip flops may be considered as:

Pf=nd*pd*f (where f is the clock frequency)

If the power estimation of a D flip flop from a technology library isunavailable, the system may still use the following formula from earlierto estimate the power consumed by a “D” type flip flop:

Pf=½Cd*ad*f*V ²

The following information may be garnered from the technology library:

Cd=Capacitance estimation of the D type flip flop

ad=Area estimation of the D type flip flop

f=clock frequency

V=Voltage for the block.

Since an RTL block may have interconnecting pins, a SystemC modelcontains interconnecting pins as well. Here, the system employs theformula

½CV².

When looking at interconnecting pins, the system may only apply theabove formula when the pin transitions from a 1-0 or from a 0-1 signalstate. Both C and V come from a technology library.

Total dynamic power consumed in the interconnects:

Pi=½CV ²*Number of pins*number of signal transitions

A number of signal transitions may be measured easily by gathering thedata from a signal transition dump file (also known as a “Value-ChangeDump” file or a VCD file). Other forms of dump file may also be used.This file may be generated when applying a stimulus to a SystemC model.

Regarding quiescent, or leakage power, because the system may determinethe number of “virtual D flip-flops” the present invention may alsoassume the amount of general quiescent power consumed along thefollowing lines:

Plf=nd*pdl where pdl is the estimated leakage power per D flip flop froma technology library.

Some of the power consumed is in the clock tree buffers. If the numberof clock nodes is known, this should be input as well, and the systemmay assume a number of buffers per node. Activity in these blocks is ata maximum level, since many clock events propagate through these buffersand accounts for power consumption. These clock buffers and the clocktree may be optionally modeled in the SystemC model. Even if notmodeled, the clock buffers may be thought of as existent for the purposeof power estimation.

Pck=Nck*Nb*pb

-   Pck=Total dynamic power consumed by the clock tree-   Nck=Number of nodes in the clock tree-   Nb=Number of clock buffers per node-   pb=Dynamic power consumed per clock tree buffer (which will be    available in a technology library). Since the SystemC model does not    contain a clock tree such as in the RTL, this information is often    used only to achieve a higher accuracy of the power estimation    number.

A SystemC model may also contain some logic that does not translate to Dflip flops. This logic might be estimated based on how many algorithmicequations exist, and how many terms are used. This can be done byparsing the code of the SystemC model. The system may estimate anapproximate “virtual gate” count for each SystemC block.

The present invention may also function to determine how many variablesmight be equated with “reg” type, and whatever is left are the non-“reg”type variables. Then, the system may determine the widths in the samemanner described for the “reg” type variables in point 9. Further, thesystem may determine the type of logical operation being done on thesevariables such as AND, OR, X-OR, and so on. Then the system may arriveat the number of those types of logical gates, determine the powerconsumption from the technology library, and determining the powerestimation for the non-“reg” type variables.

Total power consumed per clock event in the “virtual gate”

Pg=ng*p_virtual_gate*f

where f is the clock frequency.

Leakage or quiescent power for “virtual gates” may be estimated as:

Plg=ng*pgl

where ng is the estimated number of virtual gates for this SystemCblock, and pgl is the estimated leakage power per virtual gate from atechnology library.

A total power is the summation of all these calculated values:

PsystemC=Plf+Plg+Pf+Pck+Pg+Pi.

The system may log the power estimation information at pre-determinedintervals. This log information may be visualized in the form ofhistograms, bar graphs, line graphs, or in various other suitable formsof output. Any other graphical representation might be used, such as redfor high power consumption, orange, yellow and white for medium powerconsumption, and green for low power consumption.

Referring to FIG. 5, a combined data entry and waveform system for rapidbehavioral verification of digital hardware designs 500 may comprise apersonal computer 502 including a monitor 504, a storage device (such asa hard disk) 506, input devices such as a keyboard 508 and a mouse 510and peripherals, such as a printer 512. The storage device 506 may be acomputer readable storage medium.

It should be understood, of course, that the foregoing relates toexemplary embodiments of the invention and that modifications may bemade without departing from the spirit and scope of the invention as setforth in the following claims. Furthermore, a method herein describedmay be performed in one or more sequences other than the sequencepresented expressly herein.

I claim:
 1. A method for measuring power in a virtual prototype for amodel semiconductor design, the method comprising: identifying, within anetlist representing an integrated circuit, one or more transistorscoupled to a voltage supply for which to estimate power as applied to avirtual prototype representing the integrated circuit; generating arespective measurement statement for each of the one or moretransistors, wherein the respective measurement statement is usable by acircuit simulation tool to measure the power consumed within the virtualprototype of a design block during a simulation of the virtual prototyperepresenting the integrated circuit, without synthesizing the model;and, creating a measurement file and placing respective measurementstatements within the measurement file, wherein the measurement file isusable by the circuit simulation tool for performing the simulation ofthe integrated circuit.
 2. The method of claim 1, further comprising:running a simulation of the virtual prototype representing theintegrated circuit, and generating a corresponding output file;extracting, from the corresponding output file, results from at leastsome of a set of respective measurement statements; and generating apower report based on the extracted results.
 3. The method of claim 2,further comprising: performing again the method of claim
 1. 4. Themethod of claim 2, further comprising: generating a graphicalrepresentation of a power estimate for the integrated circuit based onthe power report.
 5. The method of claim 1, further comprising: runningthe simulation of the virtual prototype representing the integratedcircuit and generating a corresponding log file; extracting, from thecorresponding log file, information associated with the simulation ofthe integrated circuit; and determining whether the simulation is validbased on the extracted information.
 6. A power evaluation methodcomprising: for each respective module of a plurality of modules:providing an Electronic System Level Circuit Description (ESLCD)containing a plurality of operations of modules for analysis; reviewingthe ESLCD and identifying those operations of modules of the ESLCD thatare equivalent to a previously analyzed case, a case comprising anoperation of a module, and those operations of modules of the ESLCD thathave no equivalent previously analyzed case; for each operation ofmodule of the ESLCD that is equivalent to a previously analyzed case,retrieving a power macro-model of the previously analyzed case frommemory and assigning that power macro-model to that operation of modulein the ESLCD; for each operation of module of the ESLCD that has noequivalent previously analyzed case, generating a power macro-model foreach operation of module and assigning that generated power macro-modelto that operation of module in the ESLCD; using the plurality of powermacro-models, sample input vectors and sample output vectors, evaluatingthe power consumption of each of the operation of modules in the ESLCDand summing the power consumption of each of the operation of modules toprovide a system level power estimate; wherein the cases are defined bya circuit description and a context of the input stimuli under which thecircuit is exercised; wherein the context of the input stimuli underwhich the circuit is exercised further comprises a testbenchdescription, the testbench description partitioned into segments; andproducing a monitor file wherein the monitor file comprises the testbench description and a pair of print statements associated with eachsegment in the testbench description, in which the print statementscause the simulation time of execution of the print statement to beprinted to a designated file along with an identifier of the segment. 7.The method of claim 6, further comprising: inserting commands into anoverlay/monitor file to indicate which modules will have a powermacro-model generated from their simulated activity.
 8. The method ofclaim 7, wherein the modules identified as needing power macro-modelsare simulated and have power macro-models constructed from thesimulation.
 9. The method of claim 6, further comprising: increasing anumber of timing modes to a number greater than three.
 10. The method ofclaim 6, further comprising: parsing an object file to determinevariables.
 11. The method of claim 6, further comprising: building atable of virtual gates; and calculating estimated power from atechnology library.